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512K x 8 CMOS STATIC RAM MODULE
Integrated Device Technology, Inc.
IDT7MB4048
FEATURES:
* High-density 4-megabit (512K x 8) Static RAM module * Fast access time: 25ns (max.) Surface mounted plastic packages on a 32-pin, 600 mil FR-4 DIP substrate * Single 5V (10%) power supply * Inputs/outputs directly TTL-compatible
DESCRIPTION:
The IDT7MB4048 is a 4-megabit (512K x 8) Static RAM module constructed on a multilayer epoxy laminate (FR-4) substrate using four 1 megabit SRAMs and a decoder. The IDT7MB4048 is available with access times as fast as 25ns. The IDT7MB4048 is packaged in a 32-pin FR-4 DIP resulting in the JEDEC footprint in a package 1.6 inches long and 0.6 inches wide. All inputs and outputs of the IDT7MB4048 are TTL-compatible and operate from a single 5V supply. Fully asynchronous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use.
PIN CONFIGURATION
A 18 A 16 A 14 A 12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
FUNCTIONAL BLOCK DIAGRAM
Vcc A 15 A 17 A 13 A8 A9 A 11 A 10
ADDRESS
19 512K x 8 RAM
WE
OE
CS WE OE
CS
8 I/O
2675 drw 02
I/O7 I/O6 I/O5 I/O4 I/O3
2675 drw 01
DIP TOP VIEW
PIN NAMES
I/O0-7 A0-18 Data Inputs/Outputs Addresses Chip Select Write Enable Output Enable Power Ground
2675 tbl 01
CS WE OE
VCC GND
The IDT logo is a registered trademark of Integrated Device Technology Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
DECEMBER 1995
DSC-2675/6
7.11
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IDT7MB4048 512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE
Mode Standby Read Read Write
ABSOLUTE MAXIMUM RATINGS(1)
CS
H L L L
OE
X L H X
WE
X H H L
Output High-Z DOUT High-Z DIN
Power Standby Active Active Active
2675 tbl 02
Symbol VTERM
Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current
Commercial -0.5 to +7.0
Unit V
TA TBIAS TSTG
0 to +70 -10 to +85 -55 to +125 50
C C C mA
CAPACITANCE(1) (TA = +25C, f = 1.0MHz)
Symbol CIN CIN(C) COUT Parameter Input Capacitance Input Capacitance (CS) Output Capacitance Conditions VIN = 0V VIN = 0V VOUT = 0V Typ. Unit 35 8 35 pF pF pF
2675 tbl 03
IOUT
NOTE: 1. This parameter is guaranteed by design, but not tested.
NOTE: 2675 tbl 05 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS RECOMMENDED OPERATING Symbol Parameter Min. Typ. Max. Unit TEMPERATURE AND SUPPLY VOLTAGE
VCC GND VIH VIL Supply Voltage Supply Voltage Input High Voltage Input Low Voltage 4.5 0 2.2 -0.5(1) 5 0 -- -- 5.5 0 6 0.8 V V V V
2675 tbl 04
Grade Commercial
Ambient Temperature 0C to +70C
GND 0V
VCC 5V 10%
2675 tbl 06
NOTE: 1. VIL = -2.0V for pulse width less than 10ns.
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V 10%, TA = 0C to +70C)
7MB4048SxxP Symbol |ILI| |ILO| VOL VOH ICC ISB ISB1 Parameter Input Leakage Output Leakage Output Low Voltage Output High Voltage Dynamic Operating Current Standby Supply Current (TTL Levels) Full Standby Supply Current (CMOS Levels) Test Conditions VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC VCC = Min., IOL = 8mA VCC = Min., IOH = -1mA VCC = Max., CS VIL; f = fMAX, Outputs Open Min. -- -- -- 2.4 -- Max. Unit 8 8 0.4 -- 480 250 170 A A V V mA mA mA
2675 tbl 07
CS VIH, VCC = Max., f = fMAX,
Outputs Open
--
CS VCC - 0.2V, VIN VCC - 0.2V
or 0.2
--
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IDT7MB4048 512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 & 2
2675 tbl 09
+5 V
+5 V
480 DATAOUT 255 30 pF*
480 DATAOUT 255 5 pF*
2675 drw 04
2675 drw 05
Figure 1. Output Load
Figure 2. Output Load (for tOLZ, tCHZ, tOHZ, tWHZ, tOW and tCLZ)
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V 10%, TA = 0C to +70C)
7MB4048
-25 -30 -35
Symbol Read Cycle tRC tAA tACS tOE tOHZ(1) tOLZ
(1)
Parameter
Min. Max. 25 -- -- -- -- 0 5 -- 3 0 -- 25 17 3 20 20 15 0 0 -- 2 -- 25 25 12 12 -- -- 14 -- -- 25 -- -- -- -- -- -- -- -- 15 --
Min. Max. 30 -- -- -- -- 0 5 -- 3 0 -- 30 20 0 25 25 17 0 0 -- 5 -- 30 30 15 12 -- -- 16 -- -- 30 -- -- -- -- -- -- -- -- 15 --
Min. Max. Unit 35 -- -- -- -- 0 5 -- 3 0 -- 35 25 0 30 30 20 0 0 -- 5 -- 35 35 15 15 -- -- 20 -- -- 35 -- -- -- -- -- -- -- -- 15 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Disable to Output in High-Z Output Enable to Output in Low-Z Chip Select to Output in Low-Z Chip Deselect to Output in High-Z Output Hold from Address Change Chip Select to Power-Up Time Chip Deselect to Power-Down Time Write Cycle Time Write Pulse Width Address Set-up Time Address Valid to End-of-Write Chip Select to End-of-Write Data to Write Time Overlap Data Hold Time Write Recovery Time Output Active from End-of-Write
tCLZ(1) tCHZ(1) tOH tPU(1) tPD
(1)
Write Cycle tWC tWP tAS(2) tAW tCW tDW tDH
(2) (2)
tWR
tWHZ(1) Write Enable to Output in High-Z tOW
(1)
NOTES 1. This parameter is guaranteed by design, but not tested. 2. tAS=0ns for CS controlled write cycles. tDH, tWR= 3ns for CS controlled write cycles. 7.11
2675 tbl 10
3
IDT7MB4048 512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC ADDRESS tAA
OE
tOE tOH
CS
tOLZ tCLZ
(5)
(5)
tACS tCHZ
(5)
tOHZ
(5)
DATAOUT
2675 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC ADDRESS tAA tOH DATAOUT tOH
2675 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
CS
tACS tCLZ DATAOUT
(5)
tCHZ
(5)
2675 drw 08
NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS = VIL. 3. Address valid prior to or coincident with CS transition LOW. 4. OE = VIL. 5. Transition is measured 200mV from steady state. This parameter is guaranteed by design, but not tested.
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IDT7MB4048 512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 7) WE
tWC ADDRESS
OE
tAW
CS
tAS tWP
(7)
tWR
WE
tWHZ tOHZ DATAOUT
(4) (6) (6)
tOHZ tOW
(6) (4)
(6)
tDH tDW
DATAIN
DATA VALID
2675 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 3, 5) CS
tWC ADDRESS tAW
CS
tAS tCW tWR
WE
tDW DATAIN DATA VALID
2675 drw 10
tDH
NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of write cycle. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. Transition is measured 200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested. 7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
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IDT7MB4048 512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
PACKAGE DIMENSIONS
1.590 1.610 0.600 0.620 TOP VIEW
0.360 MAX.
SIDE VIEW
Pin 1
0.035 0.065
0.015 0.025
0.100 TYP.
0.120 0.175
0.007 0.013
0.590 0.620
BOTTOM VIEW
2675 drw 11
ORDERING INFORMATION(1)
IDT XXXX Device Type A 999 A A Process/ Temperature Range Blank Commercial (0C to +70C) Power Speed Package
P
SOJs mounted on an FR-4 DIP
25 30 35 S
Speed in Nanoseconds
Standard Power
7MB4048 512K x 8 Static RAM Module (FR-4 substrate)
2675 drw 12
7.11
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